Delta-sigma analogue to digital converters (ADCs) are well known and are commonly used in high-resolution applications because, compared to other ADC implementations, the need for complex anti-aliasing filters is reduced, differential non-linearity errors are reduced and they are more robust. By trading accuracy for speed, delta-sigma ADCs allow high performance to be achieved with high tolerance to analogue component imperfections. Delta-sigma ADCs are often seen as the best choice for low to moderate frequency, high resolution applications.
Delta-sigma ADCs can be implemented using single-bit or multi-bit feedback systems. Single-bit feedback systems are commonly used when moderate resolution is required and the master clock of the system in which the ADC is used is low-jitter. Delta-sigma ADCs with multi-bit feedback systems offer higher signal to noise ratio (SNR), lower sensitivity to jitter and in many cases lower power consumption than those with single-bit feedback systems. However, such systems require multi-bit feedback digital to analogue converters (DACs) which include multiple DAC elements. For example, a 3 bit DAC may include seven such elements in the form of current or voltage sources (one for each of the seven possible non-zero binary input values) which can be selected to generate the output voltage or current representing the binary input value.
Such a feedback DAC may suffer from “mismatch” between its elements, meaning that the values of the components making up the elements are not identical as a result of manufacturing tolerances and the like. This mismatch between the elements introduces harmonic distortion in the output of the ADC and raises the noise floor of the ADC, thereby reducing its dynamic range and SNR and increasing its total harmonic distortion (THD).
Techniques have been developed to address this problem, and one group of such techniques are known collectively as dynamic element matching (DEM). In one example of a stochastic DEM technique, elements of the feedback DAC are selected at random each clock cycle to process the DAC input. An example of a deterministic DEM technique is data weighted averaging (DWA). In this technique an algorithm is used to select different elements of the feedback DAC each clock cycle to process the DAC input. For example, in a 3 bit DAC, the input may have a binary value 011 in a first clock cycle, requiring three of the elements of the DAC to be activated to generate the required output current or voltage. In a second clock cycle the input may have changed to 001, for example, requiring only one of the elements of the DAC to be activated to generate the required output current or voltage. In this example the elements activated for the first clock cycle would be deactivated for the second clock cycle and a different element would be activated for the second clock cycle to generate the required output voltage or current, thus avoiding immediate reuse of the elements activated for the first clock cycle. In this way the effects of the mismatch are not concentrated in a single part of the frequency spectrum of the ADC, but are spread over a wider frequency range, thereby improving the SNR of the ADC and reducing its THD.
In some applications, such as high-quality audio, the input signal to the delta-sigma ADC has a very low amplitude for much of the time, such that only one of the feedback DAC elements is required to process the input. In principle no element mismatching should be experienced for such a signal, and thus there should be low harmonic distortion. However, where a DEM algorithm is used, the DEM algorithm selects a different element of the feedback DAC each clock cycle, thereby introducing additional noise, including switching noise, into the ADC, which in turn leads to a reduction in the ADC's SNR.